bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the SPP
Control Port and direction is controlled by PCD of
the Control port.
write cycle can complete. The write cycle can
complete under the following circumstances:
1. If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when
nWAIT goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go active
low before changing the state of nDATASTB,
nWRITE or nADDRSTB. The write can
complete once nWAIT is determined inactive.
In EPP mode, the system timing is closely coupled
to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The
timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (nIOR or nIOW
asserted) to nWAIT being deasserted (after
command). If a time-out occurs, the current EPP
cycle is aborted and the time-out condition is
indicated in Status bit 0.
Write Sequence of operation
1. The host selects an EPP register, places data
on the SData bus and drives nIOW active.
2. The chip drives IOCHRDY inactive (low).
3. If WAIT is not asserted, the chip must wait
until WAIT is asserted.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx bus
to always be in a write mode and the nWRITE
signal to always be asserted.
4. The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
5. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
6. Peripheral deasserts nWAIT, indicating that
any setup requirements have been satisfied
and the chip may begin the termination phase
of the cycle.
7. a) The chip deasserts nDATASTB or
nADDRSTRB, this marks the beginning
of the termination phase. If it has not
already done so, the peripheral should
latch the information byte now.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is a
logic "0" (ie a 04H or 05H should be written to the
Control port). If the user leaves PCD as a logic
"1", and attempts to perform an EPP write, the
chip is unable to perform the write (because PCD
is a logic "1") and will appear to perform an EPP
read on the parallel bus, no error is indicated.
EPP 1.9 Write
b) The chip latches the data from the SData
bus for the PData bus and asserts
(releases) IOCHRDY allowing the host to
complete the write cycle.
The timing for a write operation (address or data)
is shown in timing diagram EPP Write Data or
Address cycle. IOCHRDY is driven active low at
the start of each EPP write and is released when
8. Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been satisfied and acknowledging the
termination of the cycle.
it
has
been
determined
that
the
9. Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
90
SMSC [ SMSC CORPORATION ]
