when in PS/2 mode. In the PC/AT mode the data
bus pins D0 - D7 are held in a high impedance
state for a read of address 3F1.
STATUS REGISTER B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of
several disk interface pins in PS/2 and Model 30
modes. The SRB can be accessed at any time
PS/2 Mode
7
1
6
1
5
4
3
2
1
0
MOT
EN0
0
DRIVE WDATA RDATA WGATE MOT
SEL0 TOGGLE TOGGLE
EN1
0
RESET
COND.
1
1
0
0
0
0
BIT 0 MOTOR ENABLE 0
BIT 4 WRITE DATA TOGGLE
Active high status of the MTR0 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
Every inactive edge of the WDATA input causes
this bit to change state.
BIT 5 DRIVE SELECT 0
BIT 1 MOTOR ENABLE 1
Reflects the status of the Drive Select 0 bit of the
DOR (address 3F2 bit 0). This bit is cleared after
a hardware reset and it is unaffected by a software
reset.
Active high status of the MTR1 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 2 WRITE GATE
BIT 6 RESERVED
Active high status of the WGATE disk interface
output.
Always read as a logic "1".
BIT 7 RESERVED
BIT 3 READ DATA TOGGLE
Always read as a logic "1".
Every inactive edge of the RDATA input causes
this bit to change state.
18
SMSC [ SMSC CORPORATION ]
