GPIO OPERATION
The operation of the GPIO ports is illustrated in FIGURE 4. Note: FIGURE 4 is for illustration
purposes only and is not intended to suggest specific implementation details.
GPIO
GPIO
Configuration
Register bit-1
(Polarity)
Configuration
Register bit-0
(Input/Output)
D-TYPE
SD-bit
D
Q
GPx_nIOW
GPx_nIOR
GPIO
PIN
0
1
Transparent
0
1
Q
D
GPIO
GPIO
Configuration
Data Register
Bit-n
Register bit-2 or 5
(GROUP INT. ENABLE)
GP Group Interrupts (1 or 2)
FIGURE 4 - GPIO FUNCTION ILLUSTRATION
When a GPIO port is programmed as an input,
reading it through the GPIO data register latches
either the inverted or non-inverted logic value
present at the GPIO pin. Writing to a GPIO port
that is programmed as an input has no effect
(TABLE 54).
When a GPIO port is programmed as an output,
the logic value or the inverted logic value that has
been written into the GPIO data register is output
to the GPIO pin. Reading from a GPIO port that is
programmed as an output returns the last value
written to the data register (TABLE 54).
TABLE 54 - GPIO READ/WRITE BEHAVIOR
HOST OPERATION
GPIO INPUT PORT
GPIO OUTPUT PORT
LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA
REGISTER
READ
WRITE
NO EFFECT
BIT PLACED IN GPIO DATA
REGISTER
125
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