and Data port addresses are used to access the
GPIO data, Soft Power Status and Enable, and
the Watchdog Timer Control registers.
RUN STATE GPIO DATA REGISTER
ACCESS
The GPIO data registers as well as the Watchdog
Timer Control, and the Soft Power Enable and
Status registers can be accessed by the host
when the chip is in the run state if CR03 Bit[7] = 1.
The host uses an Index and Data port to access
these registers (TABLE 51). The Index and Data
port power-on default addresses are 0xEA and
0xEB respectively. In the configuration state the
Index port address may be re-programmed to
0xE0, 0xE2, 0xE4 or 0xEA; the Data port address
is automatically set to the Index port address + 1.
Upon exiting the configuration state the new Index
For example, to access the GP1 data register
when in the run state, the host should perform an
I/O Write of 0x01 to the Index port address (0xEx)
to select GP1 and then read or write the Data port
(at Index+1) to access the GP1 register.
Generally, to access any GPIO data register GPx
the host should perform an I/O Write of 0x0x to the
Index port address and then access GPx through
the Data port. The Soft Power and Watchdog
Timer Control registers are accessed similarly.
TABLE 51 - INDEX AND DATA PORTS
PORT
ADDRESS
PORT
NAME
Index
Data
RUN STATE ACCESS
0x01-0x0F
0xE0, E2, E4, EA
Index address + 1
Access to GP1, Watchdog Timer
Control, GP5, GP6, and the Soft
Power Status and Enable registers
(see TABLE 52).
TABLE 52 - RUN STATE ACCESSABLE CONFIGURATION REGISTERS
RUN STATE REGISTER
REGISTER (CONFIGURATION STATE ADDRESSING1)
ADDRESS (INDEX)
0x01
0x03
0x05
0x06
0x08
0x09
0x0A
0x0B
GP1 (L8 - CRF6)
Watchdog Timer Control (L8 - CRF4)
GP5 (L8 - CRF9)
GP6 (L8 - CRFA)
Soft Power Enable Register 1 (L8-CRB0)
Soft Power Enable Register 2 (L8-CRB1)
Soft Power Status Register 1 (L8-CRB2)
Soft Power Status Register 2 (L8-CRB3)
Note 1: These registers can also be accessed through the configuration registers L8 - CRxx, as shown,
when the FDC37B72x is in the configuration state.
GPIO CONFIGURATION
Each GPIO port may be configured as either an
input or an output. If the pin is configured as an
output, it can be programmed as open-drain or
push-pull. Inputs and outputs can be configured
as non-inverting or inverting and can be
programmed to generate an interrupt. GPIO ports
can also be configured as a pre-defined alternate
Each GPIO port has an 8-bit configuration register
that controls the behavior of the pin. The GPIO
configuration registers are only accessible when
the FDC37B72x is in the Configuration state; more
information can be found in the Configuration
section of this specification.
122
SMSC [ SMSC CORPORATION ]
