GENERAL PURPOSE I/O
The FDC37B72x provides
a
set of flexible
The GPIO pins can perform simple I/O or can be
individually configured to provide predefined
alternate functions. VBAT Power-On-Reset
Input/Output control functions to the system
designer through the 20 dedicated independently
programmable General Purpose I/O pins (GPIO).
configures all GPIO pins as non-inverting inputs.
DESCRIPTION
Each GPIO port requires a 1-bit data register and
an 8-bit configuration control register. The data
register for each GPIO port is represented as a bit
in one of three 8-bit GPIO DATA Registers, GP1,
GP5, and GP6. All of the GPIO registers are
located in Logical Device Block No. 8 in the
FDC37B72x device configuration space. The
GPIO DATA Registers are also optionally
available at different addresses when the
FDC37B72x is in the Run state (see the Run State
GPIO Register Access section below). The GPIO
ports with their alternate functions and
configuration state register addresses are listed in
TABLE 50. Note: four bits 1, 5-7 of GP5 are not
implemented.
TABLE 50 - GENERAL PURPOSE I/O PORT ASSIGNMENTS
DATA
DATA
REGISTER
BIT NO.
CONFIG.
REGISTER5
(HEX)
CRE0
CRE1
CRE2
CRE3
CRE4
CRE5
CRE6
CRE7
CRC8
CRCA
CRCB
CRCC
CRD0
CRD1
CRD2
CRD3
CRD4
CRD5
CRD6
CRD7
PIN NO.
QFP
77
78
79
80
81
82
4
DEFAULT
FUNCTION
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT.
FUNC. 1
nSMI
nRING
WDT
ALT.
FUNC. 2
ALT.
FUNC. 3
REGISTER5
(HEX)
GP1
(CRF6)
-
-
-
0
1
2
3
4
5
6
7
0
2
3
4
0
1
2
3
4
5
6
7
EETI1
P17/P124
EETI1
LED
-
-
-
-
-
-
-
-
IRRX2
IRTX2
nMTR1
nDS1
6
GPIO
-
-
39
2
PCI_CLK
GPIO
IRQ14
DRVDEN1 IRQ8
GPIO
-
GP5
(CRF9)
nSMI
EETI1
EETI1
nSMI
LED
nRING
WDT
P17/P124
-
91
92
83
84
85
86
87
88
89
90
nROMCS2
nROMOE2
RD02,3
RD12,3
RD22,3
RD32,3
RD42,3
RD52,3
RD62,3
RD72,3
IRQ11
IRQ12
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ10
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GP6
(CRFA)
-
-
Note 1:
Note 2:
Refer to the section on Either Edge Triggered Interrupt Inputs.
At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for
alternate functions, nROMCS must stay high until those pins are finished being programmed.
These pins cannot be programmed as open drain pins in their original function.
The function of P17 or P12 is selected via the P17/P12 select bit in the Ring Filter Select
Register in Logical Device 8 at 0xC6.
Note 3:
Note 4:
Note 5:
The GPIO Data and Configuration Registers are located in Logical Device Block Number 8.
121
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