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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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An interrupt is generated when serviceIntr is 0 and  
the number of bytes in the FIFO is less than or  
equal to <threshold>. (If the threshold = 12, then  
the interrupt is set whenever there are 12 or less  
bytes of data in the FIFO.) The PINT pin can be  
used for interrupt-driven systems. The host must  
respond to the request by writing data to the FIFO.  
If at this time the FIFO is empty, it can be  
completely filled in a single burst, otherwise a  
minimum of (16-<threshold>) bytes may be written  
to the FIFO in a single burst. This process is  
repeated until the last byte is transferred into the  
FIFO.  
Programmed I/O - Transfers from the Host to  
the FIFO  
In the forward direction an interrupt occurs when  
serviceIntr is 0 and there are writeIntrThreshold or  
more bytes free in the FIFO. At this time if the  
FIFO is empty it can be filled with a single burst  
before the empty bit needs to be re-read.  
Otherwise it may be filled with writeIntrThreshold  
bytes.  
writeIntrThreshold =  
(16-<threshold>) free  
bytes in FIFO  
106  
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