Table 8.1 Register Summary (continued)
Reg
Read
Bit 7
Bit 0
LSb
Default
Value
Reg Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock
Start
Addr
/Write
MSb
ZON2
ZON2
ZON2
RAN3
RAN3
RAN3
RES
RR2E
7
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R
R/W
R
R/W
R/W
R
PWM 1 Configuration
PWM 2 Configuration
PWM 3 Configuration
ZON1
ZON1
ZON1
RAN2
RAN2
RAN2
RES
RR2-2
6
6
6
6
6
ZON0
ZON0
ZON0
RAN1
RAN1
RAN1
RES
RR2-1
5
5
5
5
5
INV
INV
INV
RAN0
RAN0
RAN0
RES
RR2-0
4
4
4
4
4
RES
RES
RES
FRQ3
FRQ3
FRQ3
RR1E
RR3E
3
3
3
3
3
SPIN2
SPIN2
SPIN2
FRQ2
FRQ2
FRQ2
RR1-2
RR3-2
2
2
2
2
2
SPIN1
SPIN1
SPIN1
FRQ1
FRQ1
FRQ1
RR1-1
RR3-1
1
1
1
1
1
SPIN0
SPIN0
SPIN0
FRQ0
FRQ0
FRQ0
RR1-0
RR3-0
0
0
0
0
0
62h
62h
62h
C3h
C3h
C3h
E0h
00h
80h
80h
80h
5Ah
5Ah
5Ah
64h
64h
64h
44h
40h
00h
N/A
N/A
N/A
09h
09h
09h
09h
09h
09h
00h
00h
00h
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Zone 1 Range/PWM 1 Frequency
Zone 2 Range/PWM 2 Frequency
Zone 3 Range/PWM 3 Frequency
PWM1 Ramp Rate Control
PWM 2, PWM3 Ramp Rate Control
PWM 1 MINIMUM Duty Cycle
PWM 2 MINIMUM Duty Cycle
PWM 3 MINIMUM Duty Cycle
Zone 1 Low Temp Limit
Zone 2 Low Temp Limit
Zone 3 Low Temp Limit
Zone 1 Temp Absolute Limit
Zone 2 Temp Absolute Limit
Zone 3 Temp Absolute Limit
Reserved
7
7
7
7
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
RES
RES
RES
TST7
TST7
TST7
RES
RES
RES
RES
RES
RES
TST7
RES
TST7
RES
RES
RES
TST6
TST6
TST6
RES
RES
RES
RES
RES
RES
TST6
TST6
TST6
RES
RES
RES
TST5
TST5
TST5
RES
RES
RES
RES
RES
RES
TST5
TST5
TST5
RES
RES
RES
TST4
TST4
TST4
RES
RES
RES
RES
RES
RES
TST4
TST4
TST4
RES
RES
RES
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
RES
RES
RES
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
RES
RES
RES
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
RES
RES
XEN
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
Reserved
XOR Test Tree Enable
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
R/W
SMSC Test Register
Yes
SMSC [ SMSC CORPORATION ]
