Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
The results of each sampling and conversion can be found in the Reading Registers and are available
at any time, however, they are only updated once per conversion cycle.
6.4
Interrupt Status Registers
The Hardware Monitor Block contains two interrupt status registers: Register 41h: Interrupt Status
Register 1 on page 60 and on page 61. These registers are used to reflect the state of all temperature,
voltage and fan violation of limit error conditions and diode fault conditions that the Hardware Monitor
Block monitors.
When an error occurs during the conversion cycle, its corresponding bit is set in its respective interrupt
status register. The bit remains set until the register is read by software, at which time the bit will be
cleared to ‘0’ if the associated error event no longer violates the limit conditions or if the diode fault
condition no longer exists. Reading the register will not cause a bit to be cleared if the source of the
status bit remains active.
These registers are read only – a write to these registers have no effect. These registers default to
0x00 on VCC POR and Initialization.
See the description of the Interrupt Status registers in Chapter 8, "Register Set," on page 49.
Each interrupt status bit has a corresponding bit located in an interrupt enable register, which may be
used to enable/disable the individual event from setting the status bit. See the following figure for the
status and enable bits used to control the interrupt bits and INT# pin.
Revision 0.4 (04-04-05)
SMSC EMC6D103
DATA2S6HEET
SMSC [ SMSC CORPORATION ]
