Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
Table 7.1 Register Summary (continued)
Bit 7
MSb
Bit 0
LSb
Reg
Read/
Write
Default
Value
Reg Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock
Start
Addr
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
R
R
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
Reserved
V50.3
VCC.3
TST7
RES
V50.2
VCC.2
TST6
TST6
TST6
RES
V50.1
VCC.1
TST5
TST5
TST5
RES
V50.0
VCC.0
TST4
TST4
TST4
TST4
TST4
TST4
RES
V25.3
VCP.3
TST3
TST3
TST3
TST3
TST3
TST3
RES
V25.2
VCP.2
TST2
TST2
TST2
TST2
TST2
TST2
RES
V25.1
VCP.1
TST1
TST1
TST1
TST1
TST1
TST1
RES
V25.0
VCP.0
TST0
TST0
TST0
TST0
TST0
TST0
RES
N/A
N/A
N/A
4Dh
4Dh
09h
09h
N/A
00h
CCh
CCh
CCh
CCh
0Ch
No
No
No
No
Yes
No
Yes
No
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
R
R
R/W
R
RES
RES
R/W
R
RES
RES
RES
TST7
RES
TST6
RES
TST5
RES
R
R/W
R/W
R/W
R/W
R/W
Tach1 Option
STCH2 STCH1 STCH0 3EDG
STCH2 STCH1 STCH0 3EDG
STCH2 STCH1 STCH0 3EDG
STCH2 STCH1 STCH0 3EDG
MODE
MODE
MODE
MODE
GRD0
EDG1
EDG1
EDG1
EDG1
SZEN
EDG0
EDG0
EDG0
EDG0
SLOW
SLOW
SLOW
SLOW
Tach2 Option
Tach3 Option
Tach4 Option
PWM1 Option
RES
Note 7.6 Note 7.6
RES RES
Note 7.6 Note 7.6
RES RES
Note 7.6 Note 7.6
RES
OPP
OPP
OPP
GRD1
GRD1
GRD1
UPDT1 UPDT0
UPDT1 UPDT0
UPDT1 UPDT0
95h
96h
R/W
R/W
PWM2 Option
PWM3 Option
GRD0
GRD0
SZEN
SZEN
0Ch
0Ch
Yes
Yes
No
No
97h
98h
R/W
R/W
R
SMSC Test Register
SMSC Test Register
Reserved
TST7
TST7
RES
TST 6
TST 6
RES
TST 5
TST 5
RES
TST 4
TST 4
RES
TST3
TST3
RES
TST2
TST2
RES
TST1
TST1
RES
TST0
TST0
RES
5Ah
F1h
00h
N/A
Yes
Yes
No
No
No
No
No
99-FEh
FFh
R
SMSC Test Register
TST7
TST 6
TST 5
TST 4
TST3
TST2
TST1
TST0
No
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted
results.
Note 7.1 The PWMx Current Duty Cycle Registers are only writable when the associated fan is in
manual mode. In this case, the register is writable when the start bit is set, but not when
the lock bit is set.
Note 7.2 The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The
OVRID bit is always writable, both when the start bit is set and when the lock bit is set.
Note 7.3 The Interrupt status registers are cleared on a read if no events are active
Note 7.4 The INTEN bit in register 7Ch is always writable, both when the start bit is set and when
the lock bit is set.
Note 7.5 In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not
accessible except for the following: Bits[2:0] in the Special Function Register (SFTR) at
offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh.
Note 7.6 These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the
hardware.
Note 7.7 SMSC bits may be read/write bits. Writing these bits to a value other than the default value
may cause unwanted results
7.1
Undefined Registers
The registers shown in the table above are the defined registers in the part. Any reads to undefined
registers always return 00h. Writes to undefined registers have no effect and do not return an error.
SMSC EMC6D102
Revision 0.4 (04-05-05)
DATA4S7HEET
SMSC [ SMSC CORPORATION ]
