Multiple RPM-Based PWM Fan Controller for Five Fans
Datasheet
5.17
TACH Target Registers
Table 5.27 TACH Target Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
TACH Target
1 Low Byte
3Ch
R/W
16
8
4
2
1
-
-
-
F8h
TACH Target
1 High Byte
3Dh
4Ch
4Dh
5Ch
5Dh
6Ch
6Dh
7Ch
7Dh
R/W
R
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
FFh
F8h
FFh
F8h
FFh
F8h
FFh
F8h
FFh
TACH Target
2 Low Byte
16
8
4
TACH Target
2 High Byte
R/W
R
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
TACH Target
3 Low Byte
16
8
4
TACH Target
3 High Byte
R/W
R
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
TACH Target
4 Low Byte
16
8
4
TACH Target
4 High Byte
R/W
R
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
TACH Target
5 Low Byte
16
8
4
TACH Target
5 High Byte
R/W
4096 2048 1024
512
256
128
64
32
The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based
Fan Speed Control Algorithm.
The value in the TACH Target Registers will always reflect the current TACH Target value.
If one of the algorithms is enabled, setting the TACH Target Register to FFh will disable the fan driver
(set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh)
will cause the algorithm to invoke the Spin Up Routine after which it will function normally.
The Tach Target is not applied until the high byte is written. Once the high byte is written, the current
value of both high and low bytes will be used as the next Tach target.
5.18
TACH Reading Registers
Table 5.28 TACH Reading Registers
ADDR
R/W
REGISTER
B7
4096 2048 1024
16
4096 2048 1024
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Eh
R
Fan 1 TACH
512
256
128
64
32
FFh
Fan 1 TACH
Low Byte
3Fh
4Eh
R
R
8
4
2
1
-
-
-
F8h
FFh
Fan 2 TACH
512
256
128
64
32
Revision 1.1 (10-12-09)
SMSC EMC2305
DATA4S6HEET
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