Multiple RPM-Based PWM Fan Controller for Five Fans
Datasheet
5.13
Fan Max Step Registers
Table 5.23 Fan Max Step Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan 1 Max
Step
37h
47h
57h
67h
77h
R/W
-
-
32
16
8
4
2
1
10h
Fan 2 Max
Step
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
32
32
32
32
16
16
16
16
8
8
8
8
4
4
4
4
2
2
2
2
1
1
1
1
10h
10h
10h
10h
Fan 3 Max
Step
Fan 4 Max
Step
Fan 5 Max
Step
The Fan Max Step registers, along with the Update Time, control the ramp rate of the fan driver
response calculated by the RPM-based Fan Speed Control Algorithm. The value of the register
represents the maximum step size each fan driver will take between update times (see Section 5.9).
When the FSC algorithm is enabled, Ramp Rate control is automatically used. When the FSC is not
active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section 5.10).
APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM-based
Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the
programmed fan drive setting (either as determined by the RPM-based Fan Speed Control
Algorithm or by manual settings) exceeds the current fan drive setting by greater than the
Fan Step Register setting, the EMC2305 will limit the fan drive change to the value of the
Fan Step Register. It will use the Update Time to determine how often to update the drive
settings.
APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2
Register will cause the maximum fan step settings to be ignored.
The Fan Max Step registers are software locked.
5.14
Fan Minimum Drive Registers
Table 5.24 Minimum Fan Drive Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan 1
Minimum
Drive
66h
(40%)
38h
48h
58h
R/W
128
64
32
16
8
4
2
1
Fan 2
Minimum
Drive
66h
(40%)
R/W
R/W
128
128
64
64
32
32
16
16
8
8
4
4
2
2
1
1
Fan 3
Minimum
Drive
66h
(40%)
SMSC EMC2305
Revision 1.1 (10-12-09)
DATA4S3HEET
SMSC [ SMSC CORPORATION ]
