Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
6.29
Fan Drive Fail Band Registers
Table 6.44 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan 1 Drive
Fail Band
Low Byte
4Ah
R/W
16
8
4
2
1
-
-
-
00h
Fan 1 Drive
Fail Band
High Byte
4Bh
8Ah
8Bh
R/W
R/W
R/W
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
00h
00h
00h
Fan 2 Drive
Fail Band
Low Byte
16
8
4
Fan 2 Drive
Fall Band
High Byte
4096 2048 1024
512
256
128
64
32
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail
detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is
enabled, the actual measured fan speed is compared against the target fan speed. These registers
are only used when the FSC is active.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually
capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan
Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]
bits then the DRIVE_FAIL status bit will be set and an interrupt generated.
6.30
TACH Target Registers
Table 6.45 TACH Target Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
TACH Target
1 Low Byte
4Ch
R/W
16
8
4
2
1
-
-
-
F8h
TACH Target
1 High Byte
4Dh
8Ch
8Dh
R/W
R
4096 2048 1024
512
2
256
1
128
-
64
-
32
-
FFh
F8h
FFh
TACH Target
2 Low Byte
16
8
4
TACH Target
2 High Byte
R/W
4096 2048 1024
512
256
128
64
32
The TACH Target Registers hold the target tachometer value that is maintained each of the RPM based
Fan Speed Control Algorithms.
The value in the TACH Target Registers will always reflect the current TACH Target value. If the Look
Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing
to this register will have no affect and the data will not be stored.
SMSC EMC2104
Revision 1.74 (05-08-08)
DATA7S3HEET
SMSC [ SMSC CORPORATION ]
