Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
6.24
Gain Registers
Table 6.35 Gain Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Gain 1
Register
45h
85h
R/W
R/W
-
-
GAIND[1:0]
GAIND[1:0]
GAINI[1:0]
GAINI[1:0]
GAINP[1:0]
GAINP[1:0]
2Ah
Gain 2
Register
-
-
2Ah
The Gain Register stores the gain terms used by the proportional and integral portions of each of the
RPM based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain
terms in a classic PID control solution.
Table 6.36 Gain Decode
GAIND OR GAINP OR GAINI [1:0]
1
0
RESPECTIVE GAIN FACTOR
0
0
1
1
0
1
0
1
1x
2x
4x (default)
8x
6.25
Fan Spin Up Configuration Registers
Table 6.37 Fan Spin Up Configuration Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan 1 Spin Up
Configuration
DRIVE_FAIL
_CNT1 [1:0]
NOK
ICK1
SPINUP_TIM
E [1:0]
46h
R/W
SPIN_LVL[2:0]
SPIN_LVL[2:0]
0Dh
Fan 2 Spin up
Configuration
DRIVE_FAIL
_CNT2 [1:0]
NOK
ICK2
SPINUP_TIM
E [1:0]
86h
R/W
0Dh
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine. The Fan Spin Up
Configuration Register is software locked.
Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 6.38. This circuitry determines whether the fan can be driven to
the desired tach target.
SMSC EMC2104
Revision 1.74 (05-08-08)
DATA6S9HEET
SMSC [ SMSC CORPORATION ]
