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EMC2103-2-AP 参数 Datasheet PDF下载

EMC2103-2-AP图片预览
型号: EMC2103-2-AP
PDF下载: 下载PDF文件 查看货源
内容描述: 基于RPM的风扇控制器硬件过热关机 [RPM-Based Fan Controller with HW Thermal Shutdown]
分类和应用: 风扇控制器
文件页数/大小: 84 页 / 1193 K
品牌: SMSC [ SMSC CORPORATION ]
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RPM-Based Fan Controller with HW Thermal Shutdown  
Datasheet  
Table 6.49 Look Up Table Registers (continued)  
RPM /  
PWM  
ADDR  
R/W  
REGISTER  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
LUT Temp 4  
Setting 8  
7Fh  
(127°C)  
78h  
R/W  
X
X
-
64  
32  
16  
8
4
2
1
LUT Temp  
Hysteresis  
79h  
R/W  
-
-
-
16  
8
4
2
1
0Ah  
The Look Up Table Registers hold the 40 entries of the Look Up Table that controls the drive of the  
PWM. As the temperature channels are updated, the measured value for each channel is compared  
against the respective entries in the Look Up Table and the associated drive setting is loaded into an  
internal shadow register and stored.  
The bit weighting for temperature inputs represents °C and is compared against the measured data.  
Note that the LUT entry does not include a sign bit. The Look Up Table does not support negative  
temperature values and the MSBit should not be set for a temperature input.  
Each temperature channel threshold shares the same hysteresis value. When the measured  
temperature for any of the channels meets or exceeds the programmed threshold, the drive setting  
associated with that threshold is used. The temperature must drop below the threshold minus the  
hysteresis value before the drive setting will be set to the previous value.  
If the RPM based Fan Speed Control Algorithm is used, the TACH Target is updated after every  
conversion. It is always set to the minimum TACH Target that is stored by the Look Up Table. The  
PWM duty cycle is updated based on the RPM based Fan Speed Control Algorithm configuration  
settings.  
If the RPM based Fan Speed Control Algorithm is not used, then the PWM duty cycle is updated after  
every conversion. It is set to the maximum duty cycle that is stored by the Look Up Table.  
6.34  
GPIO Direction Register (EMC2103-2 Only)  
Table 6.50 GPIO Direction Register  
ADDR  
R/W  
REGISTER  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
GPIO  
Direction 1  
-
-
GPIO  
GPIO  
00h  
E1h  
R/W  
2_DIR 1_DIR  
The GPIO Direction Register controls the direction of GPIOs 1 and 2.  
Bit 1 - GPIO2_DIR - Determines the direction of GPIO2.  
„
„
‘0’ (default) - GPIO2 is configured as an input.  
‘1’ - GPIO1 is configured as an output.  
Bit 0 - GPIO2_DIR - Determines the direction of GPIO1.  
„
„
‘0’ (default) - GPIO1 is configured as an input.  
‘1’ - GPIO1 is configured as an output.  
SMSC EMC2103  
Revision 0.85 (01-29-08)  
DATA6S5HEET