High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
5.21 VSENSE Limit Registers
Table 5.33 VSENSE Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
60h
R/W
Sense Voltage
High Limit
Sign
1024
512
256
128
64
32
16
7Fh
61h
R/W
Sense Voltage
Low Limit
Sign
1024
512
256
128
64
32
16
80h
The VSENSE Limit registers store a high and low limit for VSENSE. VSENSE is compared against both
limits after each update.
The data format for the limit is a raw binary form that is relative to the maximum VSENSE that has been
programmed.
If the measured sense voltage meets or exceeds the high limit or drops below the low limit, the ALERT
pin is asserted and the VSENSE_HIGH or VSENSE_LOW status bits are set in the High Limit Status
or Low Limit Status registers (see Section 5.12 and Section 5.13).
APPLICATION NOTE: VSENSE is always checked to be greater than the high limit or less than the low limit including
when VSENSE is negative.
5.22 Source Voltage Limit Registers
Table 5.34 Source Voltage Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
64h
R/W
Source
Voltage
12
6
3
1.5
0.75
0.375
0.1875
0.0938
FFh
High Limit
65h
R/W
Source
Voltage Low
Limit
12
6
3
1.5
0.75
0.375
0.1875
0.0938
00h
The Source Voltage Limit registers store the high and low limits for VSOURCE. VSOURCE is compared
against all limits after each update.
If VSOURCE meets or exceeds the corresponding high limit or drops below the low limit, the ALERT pin
is asserted and the VSRC_HIGH or VSRC_LOW status bits are set in the High Limit Status or Low
Limit Status registers (see Section 5.12 and Section 5.13).
5.23 Critical Voltage Limit Registers
Table 5.35 Critical Voltage Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
66h
R/W
Sense Voltage
Vcrit Limit
Sign
1024
512
256
128
64
32
16
7Fh
Revision 1.2 (09-27-10)
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