Multiple Channel 1°C Temperature Sensor with Beta Compensation
Datasheet
Table 7.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
R/W
REGISTER NAME
FUNCTION
PAGE
Stores a fixed value that identifies
the device
FDh
FEh
FFh
R
Product ID
20h
5Dh
04h
Page 36
Stores a fixed value that
represents SMSC
R
R
Manufacturer ID
Revision
Page 36
Page 37
Stores a fixed value that
represents the revision number
7.1
Data Read Interlock
When any temperature channel high byte register is read, the corresponding low byte is copied into
an internal ‘shadow’ register. The user is free to read the low byte at any time and be guaranteed that
it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading
from the same high byte register again will automatically refresh this stored low byte data.
7.2
Temperature Data Registers
Table 7.2 Temperature Data Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Internal Diode
High Byte
00h
29h
01h
10h
R
128
64
32
16
8
4
2
1
00h
Internal Diode
Low Byte
R
R
R
0.5
128
0.5
0.25
64
0.125
32
-
16
-
-
8
-
-
4
-
-
2
-
-
1
-
00h
00h
00h
External Diode
High Byte
External Diode
Low Byte
0.25
0.125
As shown in Table 7.2, all temperatures are stored as an 11-bit value with the high byte representing
the integer value and the low byte representing the fractional value left justified to occupy the MSBits.
7.3
Status Register
Table 7.3 Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
02h
R-C
Status
BUSY
IHIGH
ILOW
EHIGH ELOW
FAULT
ETHERM ITHERM
00h
The Status Register reports the operating status of the Internal Diode and External Diode channels.
When any of the bits are set (excluding the BUSY bit) either the ALERT or THERM pin is being
asserted.
The ALERT and THERM pins are controlled by the respective consecutive alert counters (see
Section 7.11) and will not be asserted until the programmed consecutive alert count has been reached.
SMSC EMC1412
Revision 1.41 (02-23-12)
DATA2S7HEET
SMSC [ SMSC CORPORATION ]
