10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Chapter 3 Description of Pin Functions
PIN NO
NAME
SYMBOL
I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
44,45,
46
Address 0-2 A0/nMUX
A1
IN
IN
On a non-multiplexed mode, A0-A2 are address input bits.
(A0 is the LSB) On a multiplexed address/data bus, nMUX
tied Low, A1 is left open, and ALE is tied to the Address
Latch Enable signal. A1 is connected to an internal pull-up
resistor.
A2/ALE
IN
1,2,4,
Data 0-7
AD0-AD2,
D3-D7
I/O
On a non-multiplexed bus, these signals are used as the
lower byte data bus lines. On a multiplexed address/data
bus, AD0-AD2 act as the address lines (latched by ALE)
and as the low data lines. D3-D7 are always used for data
only. These signals are connected to internal pull-up
resistors.
7,9,
10,12, 13
47, 48,
3,5,
Data 8-15
D8-D15
I/O
D8-D15 are always used as the higher byte data bus lines
only for 16bit internal RAM access. When the 16bit access
is disabled, these signals are always Hi-Z. Enabling or
disabling the 16bit access is programmable. A data
swapper is built in. These signals are connected to internal
pull-up resistors.
14-17
37
nWrite/
nWR/DIR
nRD/nDS
IN
IN
nWR is for 80xx CPU, nWR is Write signal input. Active
Low.
Direction
DIR is for 68xx CPU, DIR is Bus Direction signal input.
(Low: Write, High: Read.)
39
nRead/
nRD is for 80xx CPU, nRD is Read signal input. Active Low.
nData Strobe
nDS is for 68xx CPU, nDS is Data Strobe signal input.
Active Low.
31
34
36
42
nReset In
nInterrupt
nChip Select
nI/O
nRESET
nINTR
IN
Hardware reset signal. Active Low.
Interrupt signal output. Active Low.
Chip Select input. Active Low.
OUT
IN
nCS
nIOCS16
OUT
This signal is an active Low signal which indicates
accessing 16bit data only by CPU. This signal becomes
active when CPU accesses to data register only if W16 bit
is 1. This signal is same as on ISA Bus signal, but it’s not
OPEN-DRAIN. An external OPEN-DRAIN Buffer is needed
when this signal connects to the ISA Bus.
16 Bit
Indicator
26
Read/Write
Bus Timing
Select
BUSTMG
IN
Read and Write Bus Access Timing mode selecting signal.
Status of this signal effects CPU and DMA Timing.
L: High speed timing mode (only for non-multiplexed bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
33
35
38
DMA
Request
DREQ
nDACK
TC
OUT
IN
DMA Request signal. Active polarity is programmable.
Default is active high.
DMA Ack
DMA Acknowledge signal. Active Low. When BUSTMG is
High, this signal is connected to internal pull-up registers
Terminal
Count
IN
Terminal Count signal. Active polarity is programmable.
Default is active high. When BUSTMG is High, this signal is
connected to the internal pull-up resistor.
40
Refresh
Execution
nREFEX
IN
Refresh execution signal. Falling edge detection. This
signal is connected to the internal pull-up resistor.
Revision 02-27-06
Page 8
SMSC COM20022I
DATASHEET