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COM20022TQFP 参数 Datasheet PDF下载

COM20022TQFP图片预览
型号: COM20022TQFP
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 外围集成电路数据传输控制器局域网时钟
文件页数/大小: 82 页 / 489 K
品牌: SMSC [ SMSC CORPORATION ]
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM  
Datasheet  
Chapter 4 Protocol Description  
4.1  
Network Protocol  
Communication on the network is based on a token passing protocol. Establishment of the network  
configuration and management of the network protocol are handled entirely by the COM20022I's internal  
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet  
and its destination ID into the COM20022I's internal RAM buffer, and issuing a command to enable the  
transmitter. When the COM20022I next receives the token, it verifies that the receiving node is ready by  
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge  
message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the  
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the  
transmitter passes the token. Once it has been established that the receiving node can accept the packet  
and transmission is complete, the receiving node verifies the packet. If the packet is received  
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received  
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful  
delivery of the packet. An interrupt mask permits the COM20022I to generate an interrupt to the processor  
when selected status bits become true. Figure 2.1 is a flow chart illustrating the internal operation of the  
COM20022I connected to a 20 MHz crystal oscillator.  
4.2  
Data Rates  
The COM20022I is capable of supporting data rates from 156.25 Kbps to 10 Mbps. The following protocol  
description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be  
doubled or quadrupled by the internal clock multiplier (see next section). For slower data rates, an internal  
clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the  
following table:  
Example:  
IDLE LINE Timeout @ 10 Mbps = 20.5 μs. IDLE LINE Timeout for 156.2 Kbps is 20.5 μs * 64 = 1.3 ms  
INTERNAL CLOCK  
TIMEOUT SCALING FACTOR  
(MULTIPLY BY)  
CLOCK PRESCALER  
DATA RATE  
FREQUENCY  
80 MHz  
Div. by 8  
Div. by 8  
10 Mbps  
5 Mbps  
1
2
40 MHz  
20 MHz  
Div. by 8  
2.5 Mbps  
4
Div. by 16  
Div. by 32  
Div. by 64  
Div. by 128  
1.25 Mbps  
625 Kbps  
312.5 Kbps  
156.25 Kbps  
8
16  
32  
64  
SMSC COM20022I  
Page 11  
Revision 02-27-06  
DATASHEET  
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