10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Figure 10.1 - Effect of the EF Bit on the TA/RI Bit........................................................................................................81
List of Tables
Table 5.1 - Typical Media .............................................................................................................................................29
Table 6.1 - Read Register Summary............................................................................................................................31
Table 6.2 - Write Register Summary ............................................................................................................................32
Table 6.3 - Status Register ...........................................................................................................................................37
Table 6.4 - Diagnostic Status Register..........................................................................................................................38
Table 6.5 - Command Register.....................................................................................................................................39
Table 6.6 - Address Pointer High Register ....................................................................................................................40
Table 6.7 - Address Pointer Low Register.....................................................................................................................41
Table 6.8 - Sub Address Register .................................................................................................................................41
Table 6.9 - Configuration Register ................................................................................................................................42
Table 6.10 - Setup 1 Register .......................................................................................................................................43
Table 6.11 - Setup 2 Register .......................................................................................................................................44
Table 6.12 - Bus Control Register.................................................................................................................................45
Table 6.13 - DMA Count Register.................................................................................................................................46
Table 8.1 - DMA Timing................................................................................................................................................76
Table 9.1 - COM20022I 48 Pin TQFP Package Parameters........................................................................................78
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes,
please refer to the ARCNET Local Area Network Standard, or the ARCNET Designer's
Handbook, available from Datapoint Corporation.
SMSC COM20022I
Page 5
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
