10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
General Description................................................................................................................6
Pin Configuration....................................................................................................................7
Description of Pin Functions ..................................................................................................8
Protocol Description .............................................................................................................11
Network Protocol........................................................................................................................................11
Data Rates .................................................................................................................................................11
Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12
Network Reconfiguration............................................................................................................................12
Broadcast Messages..................................................................................................................................13
Extended Timeout Function .......................................................................................................................13
Response Time...................................................................................................................................13
Idle Time .............................................................................................................................................13
Reconfiguration Time..........................................................................................................................13
Line Protocol ..............................................................................................................................................14
Invitations To Transmit........................................................................................................................14
Free Buffer Enquiries ..........................................................................................................................14
Data Packets.......................................................................................................................................14
Acknowledgements.............................................................................................................................15
Negative Acknowledgements..............................................................................................................15
System Description ..............................................................................................................16
Microcontroller Interface.............................................................................................................................16
Selection of 8/16-Bit Access ...............................................................................................................19
DMA Transfers To And From Internal RAM ........................................................................................19
DMA Operation ...................................................................................................................................20
DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ........................................................24
DMA Data Transfer Sequence (Memory to I/O: Write A Packet).........................................................24
High Speed CPU Bus Timing Support ................................................................................................24
Transmission Media Interface ....................................................................................................................25
Traditional Hybrid Interface.................................................................................................................26
Backplane Configuration.....................................................................................................................26
Differential Driver Configuration ..........................................................................................................28
Programmable TXEN Polarity.............................................................................................................28
Functional Description..........................................................................................................30
Microsequencer..........................................................................................................................................30
Internal Registers.......................................................................................................................................32
Interrupt Mask Register (IMR).............................................................................................................32
Data Register ......................................................................................................................................33
Tentative ID Register ..........................................................................................................................33
Node ID Register.................................................................................................................................33
Next ID Register..................................................................................................................................34
Status Register....................................................................................................................................34
Diagnostic Status Register..................................................................................................................34
Command Register .............................................................................................................................34
Address Pointer Registers ..................................................................................................................34
4.2
4.2.1
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Chapter 5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
Chapter 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
Configuration Register.....................................................................................................................35
Sub-Address Register .....................................................................................................................35
Setup 1 Register..............................................................................................................................35
Setup 2 Register..............................................................................................................................35
6.3
6.4
6.5
Bus Control Register ..................................................................................................................................36
DMA Count Register ..................................................................................................................................36
Internal RAM ..............................................................................................................................................47
6.5.1
6.5.2
6.6
6.6.1
6.6.2
Sequential Access Memory.................................................................................................................47
Access Speed .....................................................................................................................................47
Software Interface ......................................................................................................................................47
Selecting RAM Page Size...................................................................................................................48
Transmit Sequence.............................................................................................................................49
Receive Sequence..............................................................................................................................50
6.6.3
SMSC COM20022I
Page 3
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
