10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Table 6.10 - Sub Address Register
SYMBOL DESCRIPTION
These bits are undefined.
BIT
BIT NAME
7-3 Reserved
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tentative ID \ (Same
Node ID
\ as in
Setup 1
/ Config
/ Register)
Next ID
Setup 2
Bus Control
DMA Count
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
Table 6.11 - Configuration Register
BIT
BIT NAME
Reset
SYMBOL
DESCRIPTION
7
RESET
A software reset of the COM20022I 3V is executed by
writing a logic "1" to this bit. A software reset does not
reset the microcontroller interface mode, nor does it affect
the Configuration Register. The only registers that the
software reset affect are the Status Register, the Next ID
Register, and the Diagnostic Status Register. This bit
must be brought back to logic "0" to release the reset.
6
5
Command
CCHEN
TXEN
This bit, if high, enables the Command Chaining operation
of the device. Please refer to the Command Chaining
section for further details. A low level on this bit ensures
software compatibility with previous SMSC ARCNET
devices.
Chaining Enable
Transmit Enable
When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and
nTXEN pin inactive. When high, it enables the above
signals to be activated during transmissions. This bit
defaults low upon reset. This bit is typically enabled once
the Node ID is determined, and never disabled during
normal operation. Please refer to the Improved
Diagnostics section for details on evaluating network
activity.
Revision 02-27-06
Page 40
SMSC COM20022I 3V
DATASHEET
SMSC [ SMSC CORPORATION ]
