5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
t1
nRESET
nINTR
t2
Parameter
min
typ
max units
*
t1
t2
nRESET Pulse Width***
nINTR High to Next nINTR Low
5TXTL
DR**/2
4TXTL
EF = 0
EF = 1
T
*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
FIGURE 23 – TTL INPUT TIMING ON XTAL1 PIN
t1
nRESET
nINTR
t2
Parameter
min
typ
max units
*
t1
t2
nRESET Pulse Width***
nINTR High to Next nINTR Low
5TXTL
EF = 0
EF = 1
TDR**/2
4TXTL
*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
FIGURE 24 – RESET AND INTERRUPT TIMING
SMSC COM20020I 3.3V
Page 59
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
