5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
nTXEN
t4
t5
t2
t1
nPULSE1
LAST BIT
(400 nS BIT TIME)
t3
t2
t1
nPULSE2
RXIN
t6
t8
t7
Parameter
min
typ
max units
100
400
0
nS
nS
nS
nS
nS
t1
t2
t3
t4
t5
nPULSE1, nPULSE2 Pulse Width
nPULSE1, nPULSE2 Period
nPULSE1, nPULSE2 Overlap
nTXEN Low to nPULSE1 Low
+10
950
350
-10
850
250
Beginning of Last Bit Time to nTXEN High
t6
t7
t8
nS
nS
nS
RXIN Active Pulse Width
RXIN Period
RXIN Inactive Pulse Width
10
100
400
20
Note: Use Only 2.5 Mbps
FIGURE 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the hybrid)
t1
t3
t2
4.0V
50% of VDD
1.0V
XTAL1
Parameter
min
typ
max units
nS
nS
nS
t1
t2
t3
t4
t5
Input Clock High Time
Input Clock Low Time
Input Clock Period
Input Clock Frequency
Frequency Accuracy*
10
10
25
10
-200
100
40
200
MHz
ppm
+
Note*: Input clock frequency must be 20 MHz ( 100ppm or better) to use the internal Clock Multiplier.
-
t is applied to crystal oscillaton.
5
FIGURE 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the differential driver or the cable)
Revision 12-06-06
58
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
