5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Table 3 - Write Register Summary
WRITE
ADDR
00
MSB
LSB
TA/
TTA
C0
REGISTER
INTERRUPT
MASK
RI/TR1
0
0
0
EXCNAK
RECO
N
NEW
NEXTID
C1
01
02
C7
C6
AUTO-
INC
C5
0
C4
0
C3
0
C2
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
RD-
DATA
A10
A9
A8
03
A7
A6
A5
A4
A3
A2
A1
A0
04
05
D7
D6
0
D5
0
D4
0
D3
D2
D1
D0
(R/W)*
(R/W)*
SUB-
AD2
SUB-
AD1
SUB-
AD0
SUB-
AD0
TID0
NID0
SUBADR
06
RESE
T
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
TID2
SUB-
AD1
CONFIG-
URATION
TENTID
07-0
07-1
07-2
TID7
NID7
TID6
NID6
FOUR
NAKS
0
TID5
NID5
0
TID4
NID4
RCV-
ALL
TID3
NID3
CKP3
TID1
NID1
CKP1
NID2
NODEID
SETUP1
P1-
MODE
CKP2
SLOW-
ARB
07-3
07-4
0
0
0
0
0
0
0
TEST
RBUS-
TMG
0
CKUP
1
CKUP0
EF
NO-
SYNC
RCN-
TM1
RCN-
TM0
SETUP2
Note*:(R/W) This bit can be Written or Read. For more information see Appendix B.
7.2 INTERNAL REGISTERS
The COM20020I contains 14 internal registers. TABLE 2 and TABLE 3 illustrate the COM20020I register map. All
undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20020I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR
specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position
as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular
position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver
Inhibited bit, New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other
Status or Diagnostic Status bits can generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the
interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear
when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this
time. A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when
the "POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The
Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset.
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are undefined upon hardware reset. In case of READ operation, the Data Register is loaded with the contents
of COM20020I Internal Memory upon writing Address Pointer low only once.
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the
SMSC COM20020I 3.3V
Page 25
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
