5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
7.0 FUNCTIONAL DESCRIPTION
7.1 Microsequencer
The COM20020I contains an internal microsequencer which performs all of the control operations necessary to carry
out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The COM20020I derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I. The 10 MHz clock is the rate at which
the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is
loaded with the jump address from the ROM. The COM20020I contains an internal reconfiguration timer which
interrupts the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit
of the Diagnostic Status Register is set.
Table 2 - Read Register Summary
READ
REGISTER
STATUS
MSB
LSB
TA/
TTA
X
ADDR
00
RI/TRI
X/RI
X/TA
POR
TEST
RECON
TENTID
TMA
NEW
DIAG.
MY-RECON DUPID RCV- TOKEN
ACT
EXC-
NAK
01
STATUS
NEXT
ID
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
RD-DATA
A7
AUTO-
INC
X
X
X
A10
A2
A9
A1
D1
A8
A0
D0
02
03
A6
A5
A4
A3
D7
D6
0
D5
0
D4
0
D3
D2
04
05
SUB ADR
(R/W)*
(R/W)*
SUB-
AD2
SUB-
AD1
SUB-
AD0
CONFIG-
URATION
TENTID
RESET
CCHE TXEN
N
ET1
ET2
BACK-
PLANE
SUB-
AD1
SUB-
AD0
06
TID7
NID7
TID6
NID6
TID5
NID5
X
TID4
NID4
TID3
NID3
CKP3
TID2
NID2
CKP2
TID1
NID1
TID0
NID0
07-0
07-1
07-2
NODE ID
SETUP1
P1 MODE
FOUR
NAKS
RCV-
ALL
CKP1 SLOW-
ARB
NEXT ID
SETUP2
NXT ID7
NXT
ID6
NXT
ID5
NXT
ID4
NXT
ID3
NXT
ID2
NXT
ID1
NXT
ID0
07-3
07-4
RBUS-TMG
X
CKU
P1
CKUP0
EF
NO-
SYNC
RCN-
TM1
RCM-
TM2
Note*: (R/W) This bit can be Written or Read. For more information see Appendix B.
Revision 12-06-06
24
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
