3 Channel Capacitive Touch Sensor with 3 LED Drivers
Datasheet
Chapter 3 Communications
3.1
Communications
The CAP1133 communicates using the SMBus or I2C protocol.
The CAP1133 supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read
Block, and Write Block. In addition, the device supports I2C formatting for block read and block write
protocols.
3.2
System Management Bus
The CAP1133 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the CAP1133 will not stretch the clock signal.
TLOW
THIGH
THD:STA
TSU:STO
TRISE
TFALL
SMCLK
TSU:STA
THD:STA
THD:DAT
TSU:DAT
SMDATA
TBUF
S
S
P
P - Stop Condition
P
S - Start Condition
Figure 3.1 SMBus Timing Diagram
3.2.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.2.2
3.2.3
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.
The CAP1133 responds to SMBus address 0101_000(r/w).
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
Revision 1.32 (01-05-12)
SMSC CAP1133
DATA1S4HEET
SMSC [ SMSC CORPORATION ]
