3 Channel Capacitive Touch Sensor with 3 LED Drivers
Datasheet
3.2.4
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both
the Write Byte and Block Write protocols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will
ACK each data byte that it receives except the last data byte.
3.2.5
3.2.6
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1133 detects an SMBus Stop
bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
SMBus Timeout
The CAP1133 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus
where the SMCLK pin is held low, the device will timeout and reset the SMBus interface.
The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the
Configuration register (see Section 5.6, "Configuration Registers").
2
3.2.7
SMBus and I C Compatibility
The major differences between SMBus and I2C devices are highlighted here. For more information,
refer to the SMBus 2.0 and I2C specifications. For information on using the CAP1133 in an I2C system,
refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I2C Systems.
1. CAP1133 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz.
2. Minimum frequency for SMBus communications is 10kHz.
3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This
timeout functionality is disabled by default in the CAP1133 and can be enabled by writing to the
TIMEOUT bit. I2C does not have a timeout.
4. The SMBus client protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer
than 200µs (idle condition). This function is disabled by default in the CAP1133 and can be enabled
by writing to the TIMEOUT bit. I2C does not have an idle condition.
5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of
bytes to be sent in either direction. The SMBus protocol requires that an additional data byte
indicating number of bytes to read / write is transmitted. The CAP1133 supports I2C formatting only.
3.3
SMBus Protocols
The CAP1133 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive
Byte as valid protocols as shown below.
All of the below protocols use the convention in Table 3.1.
SMSC CAP1133
Revision 1.32 (01-05-12)
DATA1S5HEET
SMSC [ SMSC CORPORATION ]
