5 and 6 Channel Capacitive Touch Sensor
Datasheet
3.2.1
3.2.2
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.
The CAP1006-1 responds to SMBus address 0101_000(r/w).
3.2.3
3.2.4
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both
the Write Byte and Block Write protocols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will
ACK each data byte that it receives except the last data byte.
3.2.5
3.2.6
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1006 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
SMBus Timeout
The CAP1006 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus
where the SMCLK pin is held low, the device will timeout and reset the SMBus interface.
The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the
Configuration register (see Section 5.6).
2
3.2.7
SMBus and I C Compliance
The major difference between SMBus and I2C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.
2. The client protocol will reset if the clock is held low longer than 30ms.
3. The client protocol will reset if both the clock and the data line are high for longer than 150us (idle
condition).
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5. I2C devices support block read and write differently. I2C protocol allows for unlimited number of
bytes to be sent in either direction. The SMBus protocol requires that an additional data byte
indicating number of bytes to read / write is transmitted. The CAP1006 supports I2C formatting only.
Revision 1.1 (08-05-09)
SMSC CAP1005 / CAP1006
DATA1S4HEET
SMSC [ SMSC CORPORATION ]
