SL74HC4046
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
25 °C
to
£85
°C
£125
°C
Unit
V
-55°C
V
IH
Minimum High-Level
Input Voltage DC
Coupled
VOUT= 0.1 V or VCC-0.1 V
êIOUTê£ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
SIG , COMP
IN
IN
V
Maximum Low -Level
Input Voltage DC
Coupled
VOUT=0.1 V or VCC-0.1 V
êIOUTê £ 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
IL
SIG , COMP
IN
IN
VOH
Minimum High-Level
Output Voltage
PCPOUT, PCnOUT
V =V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IN
IH
êIOUTê £ 20 mA
V = V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage Qa-Qh êIOUTê £ 20 mA
PCPOUT, PCnOUT
V =V or V
IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
V = V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
IOZ
ICC
Maximum Input
Leakage Current
SIG , COMP
V =VCC or GND
2.0
3.0
4.5
6.0
±3.0
±7.0
±18.0
±30.0
±4.0
±9.0
±23.0 ±27.0
±38.0 ±45.0
±5.0
±11.0
mA
mA
mA
IN
IN
IN
Maximum Three-State Output in High-Impedance
Leakage Current
PC2OUT
6.0
±0.5
±5.0
±10
State
V = V or V
IH
IN
IL
VOUT=VCC or GND
Maximum Quiescent
Supply Current
(per Package)
V =VCC or GND
6.0
4.0
40
160
IN
IOUT=0mA
(VCO disabled)
Pins 3,5 and 14 at VCC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
