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SL74HC4046D 参数 Datasheet PDF下载

SL74HC4046D图片预览
型号: SL74HC4046D
PDF下载: 下载PDF文件 查看货源
内容描述: 锁相环 [Phase-Locked Loop]
分类和应用:
文件页数/大小: 12 页 / 136 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
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SL74HC4046  
comparators are essentially standard SL74HC outputs  
(comparator is TRI-STATEABLE). In normal  
operation VCC and ground voltage levels are fed to the  
loop filter. This differs from some phase detectors  
which supply a current to the loop filter and should be  
considered in the design.  
Phase Comparators  
2
All three phase comparators have two inputs,  
SIG and COMP . The SIG and COMP have a  
IN  
IN  
IN  
IN  
special DC bias network that enables AC coupling of  
input signals. If the signals are not AC coupled,  
standard SL74HC input levels are required. Both input  
structures are shown in Figure 6. The outputs of these  
Figure 6. Logic Diagram for Phase Comparators  
Phase Comparator 1  
This comparator is a simple XOR gate similar to  
the SL74HC86. Its operation is similar to an overdriven  
balanced modulator. To maximize lock range the input  
frequencies must have a 50% duty cycle. Typical input  
and output waveforms are shown in Figure 7. The  
output of the phase detector feeds the loop filter which  
averages the output voltage. The frequency range  
upon which the PLL will lock onto if initially out of lock  
is defined as the capture range.The capture range for  
phase detector 1 is dependent on the loop filter design.  
The capture range can be as large as the lock range,  
which is equal to the VCO frequency range.  
Figure 7. Typical Waveforms for PLL Using  
Phase Comparator 1  
This requires the phase detector output to be  
grounded; hence, the two input signals must be in  
phase. When the input frequency is fmax, the VCO  
input must be VCC and the phase detector inputs must  
be 180 degrees out of phase.  
To see how the detector operates, refer to  
Figure 7. When two square wave signals are applied to  
this comparator, an output waveform (whose duty  
cycle is dependent on the phase difference between  
the two signals) results. As the phase difference  
increases, the output duty cycle increases and the  
voltage after the loop filter increases. In order to  
achieve lock when the PLL input frequency increases,  
the VCO input voltage must increase and the phase  
The XOR is more susceptible to locking onto  
harmonics of the SIG than the digital phase detector  
IN  
2. For instance, a signal 2 times the VCO frequency  
results in the same output duty cycle as a signal equal  
to the VCO frequency. The difference is that the  
output frequency of the 2f example is twice that of the  
other example. The loop filter and VCO range should  
be designed to prevent locking on to harmonics.  
difference between COMPIN and SIG will increase. At  
IN  
an input frequency equal to fmin, the VCO input is at 0  
V
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