SL74HC109
AC ELECTRICAL CHARACTERISTICS
(CL
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
VCC
°
£
°
£
°
Symbol
Parameter
V
25 C to
85 C
125 C
Unit
°
-55 C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6
30
35
4.8
24
28
4.0
20
24
MHz
t
t
t
PLH, tPHL
PLH, tPHL
TLH, tTHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
ns
ns
pF
Maximum Propagation Delay , Set or Reset to Q or
Q (Figures 2 and 4)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
°
Power Dissipation Capacitance (Per Flip-Flop)
Used to determine the no-load dynamic power
Typical @25 C,VCC=5.0 V
CPD
40
pF
consumption: P
D
=CPD
V
CC2f+ICC
VCC
TIMING REQUIREMENTS
(CL
=50pF,Input t
r
=t
f
=6.0 ns)
VCC
Guaranteed Limit
°
°
£
°
£
°
Symbol
Parameter
V
25 C to -55 C
85 C
125 C
Unit
t
SU
Minimum Setup Time, J or K to
Clock (Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
ns
ns
ns
ns
ns
t
h
Minimum Hold Time, Clock to
J or K (Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
t
rec
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
t
w
w
Minimum Pulse Width, Set or
Reset (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
t
Minimum Pulse Width,Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
