SL74HC109
Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC109 is identical in pinout to the LS/ALS109. The device
inputs are compatible with standard CMOS outputs, with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs
with the next low-to-high transition of the clock. Both Q to Q outputs
ORDERING INFORMATION
are available from each flip-flop.
SL74HC109N Plastic
SL74HC109D SOIC
·
Outputs Directly Interface to CMOS, NMOS, and TTL
·
Operating Voltage Range: 2.0 to 6.0 V
°
°
T
A
= -55 to 125 C for all packages
·
·
m
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Outputs
Set
L
Reset
H
Clock
X
J
K
X
X
X
L
Q
Q
L
X
X
X
L
H
L
H*
H
L
L
X
H
H*
H
L
X
H
H
H
H
H
H
L
H
H
L
L
Toggle
No Change
H
H
H
X
H
H
X
H
L
PIN 16=VCC
H
L
No Change
PIN 8 = GND
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
