ST7669V
Driving Waveform
Figure 6.5-1 ST7669V COM/SEG Driving Waveform
ST7669V I/O PIN ITO Resister Limitation
Pin Name
ITO Resister
<100ꢀ
VDD, VDD2~VDD5, VSS,VSS1,VSS2,VSS4
V0IN, V0OUT, V0S ,XV0IN, XV0OUT ,XV0S , VgIN, VgOUT ,VgS ,Vm
<300ꢀ
<50ꢀ
VPP
A0, E_RD, RW_WR, /CS, D0 …D17, (SI), (SCL), TE
<1Kꢀ
/RST
<10Kꢀ
<1Kꢀ
IF[3:1], CLS, CSEL, /EXT
TCAP, CL, VREF
Floating
NOTE: 1. Make sure that the ITO resistance of COM0 ~ COM161 is equal, and so is it of SEG0 ~ SEG395. These
Limitations include the bottleneck of ITO layout.
2. The ITO layout suggestion is shown as below:
Figure 6.5-2 Power ITO layout suggestion
Ver 1.3
19/208
6/4/2008