ST7669V
6.3 System Control
Name
I/O
Description
Reserved for testing only.
Please fix this pin to VDD.
CLS
I
CL
I/O
I
Reserved for testing only. Leave this pin open.
CSEL
TCAP
VREF
VPP
This pin should connect to VDD.
I/O
O
I
Test pin. Please let it open.
For monitor reference voltage only. Please let it open.
When writing OTP, it needs outer power supply voltage 7.5~7.75V (>4mA) input to write successfully.
6.4 Microprocessor Interface
Name
I/O
Description
Reset input pin. When RST is “L”, and initialization is executed.
Parallel / Serial data input select input
/RST
I
IF3
H
H
H
H
L
IF2
H
H
L
IF1
H
L
MPU interface type
80 series 16-bit parallel
80 series 8-bit parallel
68 series 16-bit parallel
68 series 8-bit parallel
8-bit serial (4 line)
H
L
L
H
H
L
H
L
IF[3:1]
I
L
9-bit serial (3 line)
L
H
L
80 series 18-bit parallel
68 series 18-bit parallel
L
L
Note:
1. When fixing IF2=H & IF1=L, IF3 can be defined as parallel/Serial selection pin.
IF3=H: Parallel interface (80 8-bit); IF3=L: Serial interface (3-line)
2. Refer to Table 7.1-1.for detail interface connection.
Chip select input pin.
/CS
A0
I
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D17
become high impedance.
Register select input pin
A0 = "H": D0 to D17 or SI are display data
A0 = "L": D0 to D17 or SI are control data
** In 3-line/4-line interface this pad will be used for SCL function
Ver 1.3
16/208
6/4/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
