ST7558
MPU signal
A0
/WR
/RD
D0 to D7
N
N
Dummy
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
D(N)
D(N)
D(N+1) D(N+2)
D(N+1) D(N+2)
COLUMN ADDRESS
N
Fig.9 Read Timing
DISPLAY DATA RAM (DDRAM)
The ST7558 contains a 65X102 bit static RAM that stores the display data. The display data RAM store the dot data for the
LCD. It has a 65(8 pageX8 +1) X102, and extra ICOM. There is a direct correspondence between X-address and column
output number. It is 65-row by 102-column addressable array. Each pixel can be selected when the page and column
addresses are specified. The 65 rows are divided into 8 pages of 8 lines and 1 page of 1 line. Data is read from or written to
the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the
LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller
operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD
flicker.
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2005/10/05
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
