ST7558
W ritemode
acknowledgement
from ST7558
acknowledgement
from ST7558
acknowledgement
from ST7558
acknowledgement
from ST7558
acknowledgement
from ST7558
R
S
R
S
controlbyte
databyte
controlbyte
databyte
S 0 1 1 1 1
slaveaddress
0 A 1
A
A 0
A
A P
1 0
n>=0bytes
M SB.......................LSB
R/W
1byte
2n>=0bytes
commandword
Co
Co
R
/
W
R
Co
S
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 1 1 1 1 1 0
slaveaddress
0 0 0 0 0 0
controlbyte
databyte
Fig .7 I2C Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
0
Co
This stream may only be terminated by a STOP condition.
Busy Flag
The Busy Flag indicates whether the ST7558 is operating or not. When D7 is "H" in read status operation, this device is in
busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check
this flag before each instruction, which improves the MPU performance.
Data Transfer
The ST7558 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU
to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 8. And when reading
data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU
reads this stored data from bus holder for the next data read cycle as shown in figure 9. This means that a dummy read
cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the
data of the specified address cannot be output with the read display data instruction right after the address sets, but can be
output at the second read of data.
MPU signal
A0
/WR
D0 to D7
N
N
D(N)
D(N+1) D(N+2) D(N+3)
D(N+1) D(N+2) D(N+3)
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
D(N)
N
N+1
N+2
N+3
Fig.8 Write Timing
Ver 2.3
19/56
2005/10/05
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
