ST2202A
15.1 Sample Rate Control
PSG1LꢀandꢀPSG1Hꢀcontrolꢀtheꢀsampleꢀrate.ꢀPSG1[11~6]ꢀ
controlsꢀPWMꢀrepeatꢀtimesꢀ(usuallyꢀset=111100ꢀforꢀfourꢀ
timesꢀofꢀDACꢀreload)ꢀandꢀPSG1[5~0]ꢀusuallyꢀsetꢀ‘1’.ꢀTheꢀ
inputꢀclockꢀsourceꢀisꢀcontrolledꢀbyꢀPCK[2~0].ꢀTheꢀblockꢀ
diagramꢀisꢀshownꢀasꢀtheꢀfollowing:ꢀ
ꢀꢀꢀꢀꢀꢀꢀINH
ꢀꢀDAC[7~0]
ꢀDMD[0]
ꢀDMD[1]
PWMꢀGenerator
SampleꢀRateꢀGenerator
DAC[7~0]
PO
BD
DMD[0]
DMD[1]
PSG1[11~0]
PSG1[11~0]
Fs
Output
BDB
CK_IN
Enable
Fs
PSGCK
ꢀꢀꢀDACE
POB
Enable
Reload_DAC
Reload_DAC
ꢀ
FIGURE 15-1 DAC Diagram
ꢀ
ꢀ
ꢀ
PSGC
PSGꢀSelector
Output
PSGCK
ꢀꢀꢀꢀ
PSGCK
B6 B5 B4
RC
IN0
IN1
SYSCK/2
SYSCK/4
SYSCK/8
SYSCK/16
SYSCK
0
X
X
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OSCX
Select
PSGC[6~4]
OSCX
ꢀ
FIGURE 15-2 DAC Clock Source Control
ꢀ
ꢀ
TABLE 15-4 DAC Sample Rate Description (RCOSC = 2MHz)
DACꢀinterruptꢀfrequencyꢀ
PWMꢀfrequencyꢀ
PSGCꢀb6,ꢀb5,ꢀb4ꢀ
PSG1H,ꢀPSG1Lꢀ
8Kꢀ
32Kꢀ
32Kꢀ
100ꢀ
100ꢀ
00001111,ꢀ00111111ꢀ
00001111,ꢀ10111111ꢀ
16Kꢀ
ꢀ
ꢀ
Verꢀ2.5ꢀ
37
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
