ST2202A
15. PWM DAC
AꢀbuiltꢁinꢀPWMꢀDACꢀisꢀforꢀanalogꢀsamplingꢀdataꢀorꢀvoiceꢀ
signals.ꢀTheꢀstructureꢀofꢀDACꢀisꢀshownꢀinꢀTABLEꢀ15ꢁ1.ꢀ
ThereꢀisꢀanꢀinterruptꢀsignalꢀfromꢀDACꢀtoꢀCPUꢀwheneverꢀ
ꢀ
DACꢀdataꢀupdateꢀisꢀneededꢀandꢀtheꢀsameꢀsignalꢀwillꢀdecideꢀ
theꢀsamplingꢀrateꢀofꢀvoice.ꢀInꢀDACꢀmode,ꢀtheꢀfrequencyꢀofꢀ
RCꢀoscillatorꢀcan’tꢀlessꢀ2MꢀHz.
TABLE 15-1 Summary Of DAC Registers
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Wꢀ PSG1[7]ꢀ PSG1[6]ꢀ PSG1[5]ꢀ PSG1[4]ꢀ PSG1[3]ꢀ PSG1[2]ꢀ PSG1[1]ꢀ PSG1[0]ꢀ 0000ꢀ0000ꢀ
Wꢀ ꢁꢀ ꢁꢀ ꢁꢀ ꢁꢀ PSG1[11]ꢀ PSG1[10]ꢀ PSG1[9]ꢀ PSG1[8]ꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
Wꢀ DAC[7]ꢀ DAC[6]ꢀ DAC[5]ꢀ DAC[4]ꢀ DAC[3]ꢀ DAC[2]ꢀ DAC[1]ꢀ DAC[0]ꢀ 0000ꢀ0000ꢀ
INHꢀ DACE=1ꢀ ꢁ000ꢀ0000ꢀ
Address Name R/W Bit 7
Bit 1
Bit 0
Default
$012 PSG1L
$013 PSG1H
$014 DAC
$016 PSGC
Wꢀ
ꢁꢀ
PCK[2]ꢀ PCK[1]ꢀ PCK[0]ꢀ DMD[1]ꢀ DMD[0]ꢀ
ꢀ
ꢀ
TABLE 15-2 DAC Data Register (DAC)
Address Name R/W Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$014 DAC
Wꢀ DAC[7]ꢀ DAC[6]ꢀ DAC[5]ꢀ DAC[4]ꢀ DAC[3]ꢀ DAC[2]ꢀ DAC[1]ꢀ DAC[0]ꢀ 0000ꢀ0000ꢀ
ꢀ
Bitꢀ7~0:ꢀ ꢀ ꢀ DAC[7~0] :ꢀDACꢀoutputꢀdataꢀ
ꢀ
Note:ꢀForꢀSingleꢁPinꢀSingleꢀEndedꢀmode,ꢀtheꢀeffectiveꢀoutputꢀresolutionꢀisꢀ7ꢀbit.ꢀ
ꢀ
TABLE 15-3 DAC Control Register (PSGC)
Address Name R/W Bit 7
$016 PSGC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INHꢀ
Bit 0
Default
Wꢀ
ꢁꢀ
PCK[2]ꢀ PCK[1]ꢀ PCK[0]ꢀ DMD[1]ꢀ DMD[0]ꢀ
DACE=1ꢀ ꢀ ꢁꢀ000ꢀ0000ꢀ
ꢀ
Bitꢀ0:ꢀ ꢀ ꢀ ꢀ DACE :ꢀPSGꢀplayꢀasꢀToneꢀ(Noise)ꢀorꢀDACꢀGeneratorꢀselectionꢀbitꢀ
1ꢀ=ꢀPSGꢀisꢀusedꢀasꢀDACꢀGeneratorꢀ
0ꢀ=ꢀPSGꢀisꢀusedꢀasꢀToneꢀ(Noise)ꢀGeneratorꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ ꢀ ꢀ INH :ꢀDACꢀoutputꢀinhibitꢀcontrolꢀbitꢀ
1ꢀ=ꢀDACꢀoutputꢀinhibitꢀ
0ꢀ=ꢀDACꢀoutputꢀenableꢀ
ꢀ
Bitꢀ3~2:ꢀ ꢀ DMD[1~0] :ꢀDACꢀoutputꢀmodeꢀselectionꢀ
00ꢀ=ꢀSingleꢁPinꢀmodeꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ :ꢀ7ꢀbitꢀresolutionꢀ
01ꢀ=ꢀTwoꢁPinꢀTwoꢀEndedꢀmodeꢀ ꢀ ꢀ :ꢀ8ꢀbitꢀresolutionꢀ
10ꢀ=ꢀReservedꢀ
11ꢀ=ꢀTwoꢁPinꢀPushꢀPullꢀmodeꢀ ꢀ ꢀ ꢀ ꢀ :ꢀ8ꢀbitꢀresolutionꢀ
Verꢀ2.5ꢀ
36
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
