STK14C88
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
Not Selected
I/O
POWER
NOTES
13
H
X
X
X
X
Output High Z
Output Data
Input Data
Standby
Active
H
Read SRAM
q
n
L
H
Write SRAM
Active
X
X
L
Nonvolatile STORE
Output High Z
l
CC
2
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
L
L
H
H
H
H
o, p, q
Nonvolatile STORE
l
CC
2
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
o, p, q
Active
Nonvolatile RECALL
Note n: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
Note o: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note p: While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes.
Note q: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
b, f
HARDWARE STORE CYCLE
(V = 5.0V ± 10%)
CC
SYMBOLS
NO.
STK14C88
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
µs
ns
ns
ns
j, r
j, r
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
700
300
r, s
15
Hardware STORE Low to STORE Busy
HLBL
Note r: E and G low and W high for output behavior.
Note s: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
July 1999
5-25
SIMTEK [ SIMTEK CORPORATION ]
