欢迎访问ic37.com |
会员登录 免费注册
发布采购

STK14C88-N35 参数 Datasheet PDF下载

STK14C88-N35图片预览
型号: STK14C88-N35
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOIC-32]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器静态存储器光电二极管内存集成电路
文件页数/大小: 12 页 / 120 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
 浏览型号STK14C88-N35的Datasheet PDF文件第1页浏览型号STK14C88-N35的Datasheet PDF文件第2页浏览型号STK14C88-N35的Datasheet PDF文件第3页浏览型号STK14C88-N35的Datasheet PDF文件第4页浏览型号STK14C88-N35的Datasheet PDF文件第6页浏览型号STK14C88-N35的Datasheet PDF文件第7页浏览型号STK14C88-N35的Datasheet PDF文件第8页浏览型号STK14C88-N35的Datasheet PDF文件第9页  
STK14C88  
HARDWARE MODE SELECTION  
E
H
L
W
X
H
L
HSB  
A
- A (hex)  
0
MODE  
Not Selected  
I/O  
POWER  
NOTES  
13  
H
X
X
X
X
Output High Z  
Output Data  
Input Data  
Standby  
Active  
H
Read SRAM  
q
n
L
H
Write SRAM  
Active  
X
X
L
Nonvolatile STORE  
Output High Z  
l
CC  
2
0E38  
31C7  
03E0  
3C1F  
303F  
0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
L
L
H
H
H
H
o, p, q  
Nonvolatile STORE  
l
CC  
2
0E38  
31C7  
03E0  
3C1F  
303F  
0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
o, p, q  
Active  
Nonvolatile RECALL  
Note n: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,  
the part will go into standby mode, inhibiting all operations until HSB rises.  
Note o: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.  
Note p: While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes.  
Note q: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.  
b, f  
HARDWARE STORE CYCLE  
(V = 5.0V ± 10%)  
CC  
SYMBOLS  
NO.  
STK14C88  
PARAMETER  
UNITS NOTES  
Standard  
Alternate  
MIN  
1
MAX  
22  
23  
24  
25  
26  
t
t
t
t
t
t
t
t
STORE Cycle Duration  
10  
ms  
µs  
ns  
ns  
ns  
j, r  
j, r  
STORE  
DELAY  
RECOVER  
HLHX  
HLHZ  
HLQZ  
HHQX  
Time Allowed to Complete SRAM Cycle  
Hardware STORE High to Inhibit Off  
Hardware STORE Pulse Width  
700  
300  
r, s  
15  
Hardware STORE Low to STORE Busy  
HLBL  
Note r: E and G low and W high for output behavior.  
Note s: tRECOVER is only applicable after tSTORE is complete.  
HARDWARE STORE CYCLE  
25  
HLHX  
t
HSB (IN)  
24  
RECOVER  
t
22  
STORE  
t
26  
HLBL  
t
HSB (OUT)  
HIGH IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
23  
DELAY  
t
DQ (DATA OUT)  
DATA VALID  
July 1999  
5-25