STK14C88
b,f
SRAM READ CYCLES #1 & #2
(V = 5.0V ±± 10%)
CC
SYMBOLS
STK14C88-20
STK14C88-25
STK14C88-35
STK14C88-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
h
20
25
35
45
AVAV
i
3
Address Access Time
22
8
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
i
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
j
7
7
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
j
9
GHQZ
g
g
10
11
ELICCH
EHICCL
25
PS
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E and G both low.
Note j: Measured ± 200mV from steady state output voltage.
h, i
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
h
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
1
ELQV
11
EHICCL
t
t
6
ELQX
E
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
GLQX
t
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
July 1999
5-23
SIMTEK [ SIMTEK CORPORATION ]
