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STK14C88-N35 参数 Datasheet PDF下载

STK14C88-N35图片预览
型号: STK14C88-N35
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOIC-32]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器静态存储器光电二极管内存集成电路
文件页数/大小: 12 页 / 120 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
 浏览型号STK14C88-N35的Datasheet PDF文件第1页浏览型号STK14C88-N35的Datasheet PDF文件第2页浏览型号STK14C88-N35的Datasheet PDF文件第3页浏览型号STK14C88-N35的Datasheet PDF文件第5页浏览型号STK14C88-N35的Datasheet PDF文件第6页浏览型号STK14C88-N35的Datasheet PDF文件第7页浏览型号STK14C88-N35的Datasheet PDF文件第8页浏览型号STK14C88-N35的Datasheet PDF文件第9页  
                                   
                                     
                                        
                                          
                                             
                                              
DATA VALID  
STK14C88  
b, f  
SRAM WRITE CYCLES #1 & #2  
(V = 5.0V ± 10%)  
CC  
SYMBOLS  
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45  
NO.  
PARAMETER  
UNITS  
#1  
#2  
Alt.  
MIN  
20  
15  
15  
8
MAX  
MIN  
25  
20  
20  
10  
0
MAX  
MIN  
35  
25  
25  
12  
0
MAX  
MIN  
45  
30  
30  
15  
0
MAX  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
t
t
t
t
t
t
Write Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVAV  
AVAV  
WC  
WP  
CW  
DW  
t
t
Write Pulse Width  
WLWH  
WLEH  
t
t
Chip Enable to End of Write  
Data Set-up to End of Write  
Data Hold after End of Write  
Address Set-up to End of Write  
Address Set-up to Start of Write  
Address Hold after End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
ELWH  
DVWH  
WHDX  
ELEH  
DVEH  
EHDX  
t
t
t
t
t
0
DH  
AW  
t
t
t
15  
0
20  
0
25  
0
30  
0
AVWH  
AVEH  
t
t
t
AS  
AVWL  
AVEL  
t
t
t
0
0
0
0
WHAX  
j, k  
EHAX  
WR  
t
t
7
10  
13  
15  
WLQZ  
WZ  
t
t
5
5
5
5
WHQX  
OW  
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.  
Note l: E or W must be VIH during address transitions.  
Note m: HSB must be high during SRAM WRITE cycles.  
l, m  
SRAM WRITE CYCLE #1: W Controlled  
12  
t
AVAV  
ADDRESS  
19  
WHAX  
14  
ELWH  
t
t
E
17  
AVWH  
t
18  
AVWL  
t
13  
WLWH  
t
W
DATA IN  
15  
DVWH  
16  
WHDX  
t
t
20  
WLQZ  
t
21  
WHQX  
t
HIGH IMPEDANCE  
DATA OUT  
PREVIOUS DATA  
l, m  
SRAM WRITE CYCLE #2: E Controlled  
12  
AVAV  
t
ADDRESS  
18  
AVEL  
14  
ELEH  
19  
t
t
t
EHAX  
E
17  
AVEH  
t
13  
WLEH  
t
W
15  
DVEH  
16  
EHDX  
t
t
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
July 1999  
5-24