DATA VALID
STK14C88
b, f
SRAM WRITE CYCLES #1 & #2
(V = 5.0V ± 10%)
CC
SYMBOLS
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
20
15
15
8
MAX
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WC
WP
CW
DW
t
t
Write Pulse Width
WLWH
WLEH
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
0
DH
AW
t
t
t
15
0
20
0
25
0
30
0
AVWH
AVEH
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
0
WHAX
j, k
EHAX
WR
t
t
7
10
13
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E or W must be ≥ VIH during address transitions.
Note m: HSB must be high during SRAM WRITE cycles.
l, m
SRAM WRITE CYCLE #1: W Controlled
12
t
AVAV
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
DATA IN
15
DVWH
16
WHDX
t
t
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
l, m
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
t
t
t
EHAX
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
July 1999
5-24
SIMTEK [ SIMTEK CORPORATION ]
