STK12C68, STK12C68-5 (SMD5962-94599)
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68,
STK12C68,
STK12C68,
SYMBOLS
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
45
45
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
20
0
25
0
30
0
45
0
AVWH
AVEH
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
0
WHAX
i, j
EHAX
WR
t
t
10
13
14
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
W
t
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
t
AVAV
ADDRESS
E
14
ELEH
18
AVEL
19
EHAX
t
t
t
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 2.0
Document Control #ML0008
June, 2008
5
SIMTEK [ SIMTEK CORPORATION ]
