STK12C68, STK12C68-5 (SMD5962-94599)
Packages
V C
A P
1
V C
W
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
C
A 1 2
A 7
2
3
A6
A5
H S B
A 8
HSB
A8
A 6
A 5
A 4
A 3
4
5
A 9
A 1 1
A4
A9
6
A11
A3
A2
7
(T O P )
G
A 1 0
(TOP)
A 2
G
8
A 1
A 0
E
A1
A10
9
D Q
1 0
1 1
1 2
1 3
1 4
7
A0
DQ0
DQ1
E
D Q
0
D Q
D Q
D Q
D Q
6
DQ7
D Q
D Q
1
2
5
4
3
DQ6
V S S
28-pin SOIC
28-pin DIP
28-pin LCC
Pin Descriptions
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
12
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 5.0V, +10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
SS
Ground
Rev 2.0
Document Control #ML0008
June, 2008
2
SIMTEK [ SIMTEK CORPORATION ]
