STK12C68, STK12C68-5 (SMD5962-94599)
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68,
STK12C68,
STK12C68,
SYMBOLS
#1, #2
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55
NO.
PARAMETER
UNITS
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
g
t
, ELEH
25
35
45
55
AVAV
h
Address Access Time
25
10
35
15
45
20
55
35
AVQV
Output Enable to Data Valid
Output Hold after Address Change
GLQV
AXQX
ELQX
OE
OH
LZ
h
5
5
5
5
5
5
5
5
Address Change or Chip Enable to
Output Active
ns
ns
7
Address Change or
Chip Disable to Output Inactive
i
t
t
10
10
12
12
EHQZ
GLQX
HZ
8
9
t
t
t
t
t
t
t
t
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
0
0
0
0
0
0
ns
ns
ns
ns
OLZ
OHZ
PA
i
10
25
10
35
12
45
12
55
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
,
h
SRAM READ CYCLE #1: Address Controlledg
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E and G Controlledg
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
27
t
EHQZ
t
AVEL
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 2.0
Document Control #ML0008
June, 2008
4
SIMTEK [ SIMTEK CORPORATION ]
