STK10C68-M
DEVICE OPERATION
TheSTK10C68-Mhastwomodesofoperation: SRAM
modeandnonvolatilemode, determinedbythestateof
the NE pin. When in SRAM mode, the memory
operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to EEPROM or from EEPROM to SRAM.
LOW and G is HIGH. While any sequence to achieve
this state will initiate a STORE, only W initiation (STORE
CYCLE #1) and E initiation (STORE CYCLE #2) are
practical without risking an unintentional SRAM WRITE
that would disturb SRAM data. During a STORE cycle,
previous nonvolatile data is erased and the SRAM
contents are then programmed into nonvolatile ele-
ments. Once a STORE cycle is initiated, further input
SRAM READ
The STK10C68-M performs a READ cycle whenever E
and G are LOW and NE and W are HIGH. The address
specified on pins A0-12 determines which of the 8192
databyteswillbeaccessed. WhentheREADisinitiated
by an address transition, the outputs will be valid after
a delay of tAVQV (READ CYCLE #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ CYCLE #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for
transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W or NE is brought LOW.
and output is disabled and the DQ0-7 pins are tri-stated
until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the end
of the cycle, a READ will be performed and the outputs
will go active, signaling the end of the STORE.
HARDWARE PROTECT
The STK10C68-M offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W, and NE) remain in the STORE
conditionattheendofaSTORE cycle, asecondSTORE
cycle will not be started. The STORE (or RECALL) will
be initiated only after a transition on any one of these
signalstotherequiredstate. Inadditiontomulti-trigger
protection, the STK10C68-M offers hardware protec-
tion through VCC Sense. A STORE cycle will not be
initiated, and one in progress will discontinue, if VCC
goes below 4.0V. 4.0V is a typical, characterized
value.
The STK10C68-M is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1µF connected between DUT VCC
and VSS using leads and traces that are as short as
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
NONVOLATILE RECALL
SRAM WRITE
A RECALL cycle is performed when E, G, and NE are
LOW and W is HIGH. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes to
theRECALL state. Onceinitiated, theRECALL cyclewill
take tNLQX to complete, during which all inputs are
A write cycle is performed whenever E and W are LOW
and NE is HIGH. The address inputs must be stable
prior to entering the WRITE cycle and must remain
stable until either E or W go HIGH at the end of the
cycle. The data on pins DQ0-7 will be written into the
memory if it is valid tDVWH before the end of a W
controlled WRITE or tDVEH before the end of an E
controlled WRITE.
ignored. When the RECALL completes, any READ or
WRITE state on the input pins will take effect.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be recalled
an unlimited number of times.
ItisrecommendedthatGbekeptHIGH duringtheentire
WRITE cycle to avoid data bus contention on common
I/O lines. If G is left LOW, internal circuitry will turn off
the output buffers tWLQZ after W goes LOW.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W are
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