STK10C68-M
(VCC = 5.0V ± 10%)
READ CYCLES #1 & #2
SYMBOLS
NO.
STK10C68-35M
STK10C68-45M
STK10C68-55M
UNITS
PARAMETER
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
Chip Enable Access Time
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
AVAV
ACS
g
h
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
35
45
55
RC
3
t
Address Access Time
35
20
45
25
55
25
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
AA
4
t
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Write Recovery Time
OE
5
t
5
5
5
5
5
5
OH
6
t
LZ
i
7
t
17
17
20
20
25
25
HZ
8
t
0
0
0
0
0
0
OLZ
i
9
t
GHQZ
OHZ
e
10
11
11A
t
ELICCH
EHICCL
WHQV
PA
c,e
t
35
45
45
55
55
65
PS
t
WR
Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: NE must be high during entire cycle.
Note g: For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.
f,g,h
READ CYCLE #1
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (Data Out)
W
DATA VALID
11A
WHQV
t
f,g
READ CYCLE #2
2
AVAV
t
ADDRESS
1
ELQV
t
11
EHICCL
t
6
ELQX
E
G
t
7
t
4
EHQZ
t
GLQV
9
8
t
t
GHQZ
GLQX
DQ (Data Out)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
W
11A
WHQV
t
4-13
SIMTEK [ SIMTEK CORPORATION ]
