STK11C68-M
DEVICE OPERATION
The STK11C68-M has two separate modes of opera- previous nonvolatile data is first performed, followed
tion: SRAM mode and nonvolatile mode. In SRAM by a program of the nonvolatile elements. The pro-
mode, the memory operates as an ordinary static gram operation copies the SRAM data into nonvolatile
RAM. Innonvolatileoperation, dataistransferredfrom elements. Once a STORE cycle is initiated, further
SRAM to EEPROM or from EEPROM to SRAM. In this input and output are disabled until the cycle is com-
mode SRAM functions are disabled.
pleted.
SRAM READ
Because a sequence of reads from specific addresses
The STK11C68-M performs a READ cycle whenever is used for STORE initiation, it is important that no
E and G are LOW while W is HIGH. The address otherreadorwriteaccessesinterveneinthesequence
specified on pins A0-12 determines which of the 8192 or the sequence will be aborted and no STORE or
data bytes will be accessed. When the READ is RECALL will take place.
initiated by an address transition, the outputs will be
valid after a delay of tAVQV (READ CYCLE #1). If the To initiate the STORE cycle the following READ se-
READ is initiated by E or G, the outputs will be valid at quence must be performed:
t
ELQV or at tGLQV, whichever is later (READ CYCLE #2).
1. Read address 0000 (hex)
2. Read address 1555 (hex)
3. Read address 0AAA (hex)
4. Read address 1FFF (hex)
5. Read address 10F0 (hex)
6. Read address 0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE Cycle
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although
it is not necessary that G be LOW for the sequence to
be valid. After the tSTORE cycle time has been fulfilled,
theSRAMwillagainbeactivatedforREADandWRITE
operation.
The STK11C68-M is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1µF connected between DUT VCC
and VSS using leads and traces that are as short as
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
HARDWARE PROTECT
SRAM WRITE
The STK11C68-M offers hardware protection against
inadvertent STORE cycles through VCC Sense. A
STORE cycle will not be initiated, and one in progress
will discontinue, if VCC goes below 4.0V. 4.0V is a
typical, characterized value. The datasheet specifica-
tions are guaranteed only for VCC = 5.0 +10%.
A write cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W go HIGH at the end of the cycle. The
data on pins DQ0-7 will be written into the memory if it
is valid tDVWH before the end of a W controlled WRITE
or tDVEH before the end of an E controlled WRITE.
NONVOLATILE RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ op-
erations must be performed:
It is recommended that G be kept HIGH during the
entire WRITE cycle to avoid data bus contention on
commonI/Olines. IfGisleftLOW, internalcircuitrywill
turn off the output buffers tWLQZ after W goes LOW.
NONVOLATILE STORE
1. Read address 0000 (hex)
2. Read address 1555 (hex)
3. Read address 0AAA (hex)
4. Read address 1FFF (hex)
5. Read address 10F0 (hex)
6. Read address 0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
The STK11C68-MSTORE cycle is initiated by execut-
ing sequential READ cycles from six specific address
locations. By relying on READ cycles only, the
STK11C68-M implements nonvolatile operation while
remaining pin-for-pin compatible with standard 8Kx8
SRAMs. During the STORE cycle, an erase of the
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SIMTEK [ SIMTEK CORPORATION ]
