SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI3114 Pin Descriptions
PCI 66MHz 32-bit
PCI Address and Data
Pin Names: PCI_AD[31..00]
Pin Numbers: 104-109, 112, 113, 116-118, 123-127, 142, 143, 146, 147, 150, 151, 153, 154, 160-167
Address and Data buses are multiplexed on the same PCI pins. A bus transaction consists of an address phase
followed by one or more data phases. PCI supports both read and write bursts. The address phase is the first
clock cycle in which PCI_FRAME_N signal is asserted. During the address phase, PCI_AD[31:0] contain a
physical address (32 bits). For I/O, this can be a byte address. For configuration and memory it is a dword
address. During data phases, PCI_AD[7:0] contain the least significant byte (LSB) and PCI_AD[31:24] contain the
most significant byte (MSB). Write data is stable and valid when PCI_IRDY_N is asserted; read data is stable and
valid when PCI_TRDY_N is asserted. Data is transferred during those clocks where both PCI_IRDY_N and
PCI_TRDY_N are asserted.
PCI Command and Byte Enables
Pin Names: PCI_CBE[3..0]
Pin Numbers: 114, 128, 141, 155
Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction,
PCI_CBE[3:0]_N define the bus command. During the data phase, PCI_CBE[3:0]_N are used as Byte Enables.
Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data.
PCI ID Select
Pin Name: PCI_IDSEL
Pin Number: 115
This signal is used as a chip select during configuration read and write transactions.
PCI Frame Cycle
Pin Name: PCI_FRAME_N
Pin Number: 129
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. PCI_FRAME_N
is asserted to indicate that a bus transaction is beginning. While PCI_FRAME_N is asserted, data transfers
continue. When PCI_FRAME_N is deasserted, the transaction is in the final data phase or has completed.
PCI Initiator Ready
Pin Name: PCI_IRDY_N
Pin Number: 130
Initiator Ready indicates the initializing agent’s (bus master’s) ability to complete the current data phase of the
transaction. This signal is used with PCI_TRDY_N. A data phase is completed on any clock when both
PCI_IRDY_N and PCI_TRDY_N are sampled as asserted. Wait cycles are inserted until both PCI_IRDY_N and
PCI_TRDY_N are asserted together.
PCI Target Ready
Pin Name: PCI_TRDY_N
Pin Number: 136
Target Ready indicates the target agent’s ability to complete the current data phase of the transaction.
PCI_TRDY_N is used with PCI_IRDY_N. A data phase is completed on any clock when both PCI_TRDY_N and
PCI_IRDY_N are sampled asserted. During a read, PCI_TRDY_N indicates that valid data is present on
PCI_AD[31:0]. During a write, it indicates the target is prepared to accept data.
PCI Device Select
Pin Name: PCI_DEVSEL_N
Pin Number: 135
Device Select, when actively driven, indicates the driving device has decoded its address as the target of the
current access. As an input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been
selected.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
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