SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Reading and Writing of Task File and Device Control Registers
48-Bit LBA Addressing
The SiI3114 supports 48-bit LBA. The SiI3114 does not differentiate a non-extended command (one that does not
use 48-bit LBA address) from an extended command (one that uses the 48-bit LBA address). The "expanded"
registers can be read with the HOB bit of the Device Control register se to '1'.
Device Control Register and Soft Reset
When the Device Control register is written, a Register FIS for Control will be sent downstream upon one of the
following conditions:
• There is a change in the SRST bit, or;
• With SRST bit being '0', there is a change in the NIEN bit.
Note that:
• When the SRST is '1', the NIEN bit in the Register FIS sent is insignificant.
• Any change in the HOB bit will not initiate any Register FIS to be sent. In fact, HOB bit is always '0' in the
Register FIS sent.
• If the Serial ATA channel is in PARTIAL or SLUMBER state, a COMWAKE will be automatically initiated to
wake up the channel before the Register FIS is sent. However, the channel will stay at the ON state at the
end of the operation, even if no soft reset occurs.
A soft reset will do the following:
• Wake up the downstream Serial ATA device from ATA IDLE, STANDBY or SLEEP.
LED Support
The SiI3114 supports four activity LEDs via four 12mA open-drain drivers LED[0..3]. LED0 is to indicate activity in
channel 0; LED1 in channel 1; LED2 in channel 2; and LED3 in channel3.
When there is activity for a non-ATAPI device, as indicated by:
• BSY in the ATA Status being set, or;
• Any bit in the Serial ATA SActive register being set
… the corresponding LED driver outputs will be driven low.
There is no activity LED support for ATAPI device. If the downstream device is an ATAPI device, the
corresponding LED output will not be driven low.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
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