SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
7. Phased Locked Loop (PLL)
7.1 PLL Connections
The SiI 0680A ASIC utilizes an on-chip Phase Locked Loop (PLL) for high frequency clock synthesis. The PLL is designed to
generate a 400 MHz internal clock, which is divided down to produce the clocks for the ATA UDMA interface logic, and is
further divided down to produce 33 MHz for the system logic.
7.1.1 PLL Schematic
The schematic of PLL related components are shown in Figure 7-1. Reference Designators shown are for illustration purposes
only and do not reflect those on the evaluation board. The values are subject to change. Please contact Silicon Image for the
latest revision of the schematic for current reference designators and component values used on evaluation boards.
Figure 7-1: Schematic of PLL Circuitry
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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